Exemplary embodiments of the present invention relate to a semiconductor design technique, and more particularly, to a pipe latch circuit sequentially latching a plurality of data signals in response to an input/output (I/O) strobe signal.
Semiconductor memory devices such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM) perform read/write operations in response to an instruction externally inputted from a chip set. Among several circuits required to perform the read/write operations, there is a pipe latch circuit for efficiently controlling the data signals. Generally, the pipe latch circuit serially latches the data signals inputted in parallel in response to a pipe input control signal and outputs the data signals in parallel in response to a pipe output control signal.
FIG. 1 is a block diagram illustrating a known semiconductor memory device including a pipe latch circuit.
The semiconductor memory device includes a source signal generation unit 110, a control signal output unit 120, a pipe latch unit 130 including six pipe latches, and a data pad 140.
The source signal generation unit 110 generates a source signal SRC<0:5> reset in response to a reset signal RSTB and sequentially activated in response to an input/output (I/O) strobe signal IO_STBP. Herein, the I/O strobe signal IO_STBP is a control signal for transmitting a data signal loaded on a local I/O line to a global I/O line for the read operation of the semiconductor memory device. The reset signal RSTB for initializing the pipe latches is activated for an initial operation of the semiconductor memory device and a power down mode.
The control signal output unit 120 outputs a pipe input control signal PINB<0:5> based on the source signal SRC<0:5>. The pipe input control signal PINB<0:5> is generated by propagating the source signal SRC<0:5> through a plurality of inverters.
The pipe latch unit 130 sequentially latches the data signals transmitted through the global I/O line GIO in response to the pipe input control signal PINB<0:5> and outputs the data signals to the data pad 140 in response to a pipe output control signal POUT<0:5>. The width, in bits, of the source signal SRC<0:5>, the pipe input control signal PINB<0:5>, and the pipe output control signal POUT<0:5> is equal to the number of the pipe latches included in the pipe latch unit 130. The present embodiment shown in FIG. 1 includes six pipe latches in the pipe latch unit 130, and thus, the source signal SRC<0:5>, the pipe input control signal PINB<0:5>, and the pipe output control signal POUT<0:5> each have a width of six bits.
The control signal output unit 120 and the pipe latch unit 130 are generally arranged in the center of a peripheral area where the data pad 140 is also arranged. The source signal SRC<0:5> generated by the source signal generation unit 110 is transmitted to the control signal output unit 120 through relatively long transmission lines. More specifically, a relatively long transmission line for each bit of the source signal SRC<0:5> is placed in the peripheral area. Therefore, these transmission lines may be a burden when designing the peripheral area.
FIG. 2 is a circuit diagram illustrating the source signal generation unit 110 and the control signal output unit 120 shown in FIG. 1.
The source signal generation unit 110 includes a shift unit 210, a delay unit 220, and an output unit 230. The shift unit 210 is reset in response to the reset signal RSTB, and generates a shift signal K<0:5> in response to the I/O strobe signal IO_STBP. The shift unit 210 includes six flip-flops for generating the shift signal K<0:5> with a width of six bits. The delay unit 220 delays the I/O strobe signal IO_STBP, and generates a delayed I/O strobe signal D_STBP. The output unit 230 generates the source signal SRC<0:5> based on the shift signal K<0:5> in response to the delayed I/O strobe signal D_STBP. The control signal output unit 120 includes a plurality of inverters for generating the pipe input control signal PINB<0:5> based on the source signal SRC<0:5>.
FIG. 3 is a waveform diagram illustrating an operation of the source signal generation unit 110 shown in FIG. 2.
The shift unit 210 performs a shift operation in response to the I/O strobe signal IO_STBP, and accordingly, each bit of the shift signal K<0:5> is sequentially activated. Before performing the shift operation, the flip-flops are reset in response to the reset signal RSTB. The sixth shift signal K<5> is reset to a logic high level and the other shift signals K<0:4> are reset to a logic low level.
The I/O strobe signal IO_STBP is delayed by the delay unit 220 and outputted as the delayed I/O strobe signal D_STBP. The delayed I/O strobe signal D_STBP and the shift signal K<0:5> are combined by the output unit 230 to generate the source signal SRC<0:5>. The reason for generating the source signal SRC<0:5> by using the delayed I/O strobe signal D_STBP instead of the I/O strobe signal IO_STBP is to obtain a margin for combining the shift signal K<0:5>. The source signal SRC<0:5> is outputted as the pipe input control signal PINB<0:5> by the control signal output unit 120.
The pipe latch unit 130 sequentially latches the data signals inputted through the global I/O line in response to the pipe input control signal PINB<0:5>, and outputs the data signals to the data pad 140 in response to the pipe output control signal POUT<0:5>.
As the semiconductor memory device is improved to perform high speed operations and to store a large amount of information, the number of the pipe latches required in the pipe latch unit increases. When the number of the pipe latches increases, the width of the source signal SRC<0:5> and the pipe input control signal PINB<0:5> increases, and accordingly, the number of the transmission lines for transmitting the source signal SRC<0:5> and the pipe input control signal PINB<0:5> also increases. Moreover, the length of the transmission lines for transmitting the source signal SRC<0:5> to the control signal output unit 120 is relatively long. Therefore, the increase of the number of the relatively long transmission lines contributes to the undesired increase of the peripheral area and the chip size of the semiconductor memory devices.